1. Technical Field
The present invention generally concerns microprocessor and coprocessor architectures, and in more particular concerns an architecture that enables multiple coprocessors to operate in parallel to perform a wide array of data manipulation and processing tasks.
2. Background Information
Most microprocessors and microcontrollers comprise architectures that enable these components to be implemented in a variety of different systems that are designed to be used for a range of applications. However, because they are designed to support such diverse implementations, the performance of these microprocessors and microcontrollers under application-specific implementations is substantially reduced. In particular, it is desired to provide architectures that provide a high level of performance when implemented in programmable data manipulation systems while enabling support of a range of applications.
In attempting to address this problem, various processor architectures have been developed, including programmable DSPs (Digital Signal Processors). DSPs successfully support a range of digital signal processing algorithms, and are well-suited for applications in which digital signals must be rapidly processed. However, these devices are poor engines for many communication tasks often encountered in data manipulation systems.
Microprocessors such as the ARM and MIPS provide a general-purpose processor with the ability to attach coprocessors to perform application-specific functions, such as the foregoing communication tasks. This is because the general-purpose nature of the processor architecture makes it a poor choice for performing these tasks on its own. When coprocessors are implemented for such application-specific tasks, the coprocessors typically use the same instruction stream as the microprocessor. By utilizing the same instruction stream and data paths as the microprocessor, this architectures reduce the data I/O capabilities of the microprocessor. In addition, these scheme results in underutilization of both the processor and the coprocessor, since one is essentially at idle when the other is performing functions related to a particular instruction or set of instructions.
Tensilica has approached this problem by providing a configurable general-purpose microprocessor, whose instructions set can be extended to provide for application-specific tasks. While this scheme solves some of the problems that general-purpose processors suffer from, it doesn't solve some of the other problems discussed above.
In addition, some network processors incorporate microcontrollers on the data path that are fine tuned for particular applications, such as buffer management, header processing, and prioritization. While these devices provide very specific application support, they suffer from the lack of ability to easily enhance microcontrollers for other applications.